MIPS Machine Instructions

All MIPS instructions are 32 bits. Machine instructions are in binary, all fields of the instruction are translated: the operation is translated into a 6 bit number, register mneumonics ($t's, $v's, etc.) are translated into register numbers ($7, $15, etc.), and labels are translated into numbers. For branch statement, the number is the count of statements from the branch instruction to the branch target (the label to which the statement will branch). When we look at machine instructions it's easier to look at them in hex. The translation of instructions from binary to hex is explained at the end of this handout.

I-Type Instructions

I-type instructions are those with an immediate field that is used to contain an immediate operand, a branch target offset (for branch instructions), or a displacement for a memory operand (for load and store instructions). These instructions have the following fields:

• bits 31 to 26: opcode
• bits 25 to 21: Rs (source register)
• bits 20 to 16: Rt (dest register)
• bits 0 to 15: immediate operand

+-------------------------------------------------------------------+
|            |          |          |                                |
|   opcode   |    Rs    |    Rt    |              immed             |
|            |          |          |                                |
+-------------------------------------------------------------------+
 31        26 25      21 20      16 15                             0
 

Some I-type opcodes are shown below:

Examples

Assembler instruction:

     addi     $t4, $t5, 25
   opcode     Rt   Rs  immed

Machine instruction:

• addi: 001000
• $t4: reg 12 (01100₂)
• $t5: reg 13 (01101₂)
• 25₁₀: 11001₂

     001000 01101 01100 0000 0000 0001 1001
     opcode   Rs    Rt        immed
     21 ac 00 19

Branch Instructions

Branch instructions are also I-type instructions. Normally, after each instruction the PC is incremented by 4, which is the address of the next instruction in memory. A branch instruction changes the value in the PC, so that control is transfered to a different instruction. Recall that an address is 32 bits; this cannot be included in a 32 bit instruction. For branch instructions, what is included is a displacement: the number of bytes between the current instruction and the branch target. This displacement is positive if the branch target is an instruction that comes later in the program, and the displacement is negative if the branch target is an instruction that appears earlier than the branch instruction itself. The displacement is specified in words, not bytes, so the 16 bit immediate operand field allows displacements from -32768 words to 32767 words.

Because of pipelining, the PC is incremented by 4 after an instruction is fetched but before it is executed. The immediate operand in a branch instruction takes account of this. Therefore if the displacement is positive then the displacement in the immediate field is (the actual displacement - 1), and if the displacement in the immediate field is negative then the displacement in the immediate field is (the actual displacement + 1).

The branches that compare with zero, such as bgtz and blez, only use one register, Rs. The field for Rt contains a code that supplements the opcode in encoding the branch instruction.

The opcodes for the branch instructions are given below.

Examples

Assembler instruction:

     bgtz     $t1, skip
   opcode     Rs   immed

Machine instruction:

Here are two versions of the instruction. The immediate operand is determined by the number of statements from the branch statement to the branch target (the label to which the statement may branch). If the branch target is after the branch statement, the immediate operand is positive; if the branch target is before the branch statement, the immediate operand is negative. In both cases you must subtract one from the number of statements to get the immediate operand.

• bgtz: 000111
• $t1: reg 9 (01001₂)
• code: 00000
• skip: depends on where this label is relative to the branch instr; suppose it is 5 statements later, then the immed operand is 5 - 1 = 4

     000111 01001 00000 0000 0000 0000 0100
     opcode   Rt    code        immed
     1d 20 00 04

• bgtz: 000111
• $t1: reg 9 (01001₂)
• code: 00000
• skip: depends on where this label is relative to the branch instr; suppose it is 9 statements before the branch, then the immed operand is -9 - 1 = -10

     000111 01001 00000 1111 1111 1111 0110
     opcode   Rt    code        immed
     1d 20 ff f6

R-Type Instructions

R-type instructions are shift instructions and those with three register operands. These instructions all use opcode 000000. The actual operation is specified by the function field. Any unused fields in the instruction are set to all zero bits. R-type instructions have the following fields:

• bits 31 to 26: opcode
• bits 25 to 21: Rs (source register 1)
• bits 20 to 16: Rt (source register 2)
• bits 15 to 11: Rd (dest register)
• bits 10 to 6: shift amount (for shift instrs)
• bits 5 to 0: function (supplement to opcode)

+---------------------------------------------------------------------+
|            |          |          |          |          |            |
|   opcode   |    Rs    |    Rt    |    Rd    | shiftamt |    func    |
|            |          |          |          |          |            |
+---------------------------------------------------------------------+
 31        26 25      21 20      16 15      11 10       6 5         0

Some R-type opcodes are shown below:

Examples

Assembler instruction:

     sub      $t3, $t2, $t1
   opcode     Rd   Rs   Rt

Machine instruction:

• sub: 000000
• $t3: reg 11 (01011₂)
• $t2: reg 10 (01010₂)
• $t1: reg 9 (01001₂)
• code: 100010

     000000 01010 01001 01011 00000 100010
     opcode   Rs    Rt    Rd         code
     01 49 58 22

Assembler instruction:

     sll      $s2, $s5, 6
   opcode     Rd   Rt   sa

Machine instruction:

• sll: 000000
• $s2: reg 18 (10010₂)
• $s5: reg 21 (10101₂)
• sa: 6 (00110₂)
• code: 000000

     000000 10101 10010 00000 00100 000000
     opcode   Rs    Rt         sa    code
     02 B2 01 00

Machine Instructions in Hex

Machine instructions are in binary, which makes them hard for us to work with. We can use hex as a shorthand to represent the instructions, but we need to be careful. The fields of the instructions are not in groups of 4 bits, which is what we need to translate binary to hex. Be sure that when you translate to hex, you ignore the fields of the instruction and take groups of 4 bits.

Examples:

     sll      $s2, $s5, 6
     000000 10101 10010 00000 00100 000000
     0000 | 0010 | 1011 | 0010 | 0000 | 0001 | 0000 | 0000
     02 B2 01 00

     sub      $t3, $t2, $t1
     000000 01010 01001 01011 00000 100010
     0000 | 0001 | 0100 | 1001 | 0101 | 1000 | 0010 | 0010
     01 49 58 22

     addi     $t4, $t5, 25
     001000 01101 01100 0000 0000 0001 1001
     0010 | 0001 | 1010 | 1100 | 0000 | 0000 | 0001 | 1001
     21 ac 00 19

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