CSC263 Comp Org/Arch - MIPS Opcodes

MIPS Opcodes

Some I-type opcodes are shown below:

Assembler Instruction	Machine Opcode	Notes
addi Rt, Rs, Immed	001000
andi Rt, Rs, Immed	001100
ori Rt,Rs,Immed	001101
xori Rt, Rs, Immed	001110

The opcodes for the branch instructions are given below.

Assembler Instruction	Machine Opcode	Notes
beq Rs,Rt,Label	000100
bgez Rs, Label	000001	Rt: 00001
bgtz Rs, Label	000111	Rt: 00000
blez Rs, Label	000110	Rt: 00000
bltz Rs, Label	000001	Rt: 00000
bne Rs,Rt,Label	000101

Some R-type opcodes are shown below:

Instruction	ShiftAmt	Function	Notes
add Rd,Rs,Rt	00000	100000
and Rd,Rs,Rt	00000	100100
nor Rd,Rs,Rt	00000	100111
or Rd,Rs,Rt	00000	100101
sub Rd,Rs,Rt	00000	100010
xor Rd,Rs,Rt	00000	100110
sll Rd,Rt,sa	sa (5 bit unsigned binary)	000000	Rs: 00000
sllv Rd,Rt,Rs	00000	000100
sra Rd,Rt,sa	sa (5 bit unsigned binary)	000011	Rs: 00000
srav Rd,Rt,Rs	00000	000111

MIPS Machine Instruction Formats

I-Type Instructions

+-------------------------------------------------------------------+
|            |          |          |                                |
|   opcode   |    Rs    |    Rt    |              immed             |
|            |          |          |                                |
+-------------------------------------------------------------------+
 31        26 25      21 20      16 15                             0

bits 31 to 26: opcode
bits 25 to 21: Rs (source register)
bits 20 to 16: Rt (dest register)
bits 0 to 15: immediate operand

R-Type Instructions

+---------------------------------------------------------------------+
|            |          |          |          |          |            |
|   opcode   |    Rs    |    Rt    |    Rd    | shiftamt |    func    |
|            |          |          |          |          |            |
+---------------------------------------------------------------------+
 31        26 25      21 20      16 15      11 10       6 5         0

bits 31 to 26: opcode
bits 25 to 21: Rs (source register 1)
bits 20 to 16: Rt (source register 2)
bits 15 to 11: Rd (dest register)
bits 10 to 6: shift amount (for shift instrs)
bits 5 to 0: function (supplement to opcode for some instrs)