RISC


Three key characteristics of RISC (Reduced Instruction Set Computer):

  1. large number of registers
  2. limited and simple instruction set
  3. emphasis on optimizing the instruction pipeline

Large Number of Registers

A memory access can take as much as 100 to 500 times the time for the cpu to execute an instruction. If data used in computation is already in a register, then there is no need for a memory access. If the processor does not need to wait for memory, then the processor is busier, which results in better performance.

Simple Instruction Set

Emphasis on Instruction Pipelining

Instructions are executed in the fetch-execute cycle. If the computer waits till the end of one cycle to start the next, then components are idle during different parts of the cycle. If the cycles are overlapped then the machine can get instructions through more quickly and get more done: while decoding one instruction, fetch the next; while executing one instruction, decode the next.

Here is a conceptual view of pipelining. We will discuss MIPS pipelining in more detail.

Instr 1 fetch instr decode instr fetch operands execute
Instr 2 fetch instr decode instr fetch operands execute
Instr 3 fetch instr decode instr fetch operands execute

Common Characteristics of RISC Systems

  1. single instruction size, usually 4 bytes
  2. small number of data addressing modes
  3. no indirect addressing that requires a memory access to get the address of an operand in memory
  4. no arithmetic with operands in memory
  5. no more than one operand in memory per instruction
  6. no support for arbitrary data alignment for loads and stores

Comparison of Some RISC and CISC Machines

  CISC RISC
  IBM 370/168 Intel 486 SPARC MIPS R4000
Year 1973 1989 1987 1991
Number of Instructions 208 235 69 94
Instruction Size 2 - 6 1 - 11 4 4
Addressing Modes 4 11 1 1
Number of Registers 16 8 40 - 520 32

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