MIPS contains shift operators in addition to the bit-manipulation operations. Shift instructions move the bits to the right or left within a register.
A left shift moves every bit to the left. A zero is shifted into the low order bit and the high order bit is lost. For example, consider the following example of left shift using a 16 bit operand:
original: 0011 0100 1101 1110 (0011010011011110)
shift left 1: 0110 1001 1011 1100 (0110100110111100)
shift left 2: 1101 0011 0111 1000 (1101001101111000)
shift left 3: 1010 0110 1111 0000 (1010011011110000)
shift left 4: 0100 1101 1110 0000 (0100110111100000)
Shifting 1 bit to the left is equivalent to multiplication by 2. Shifting n bits to the left is equivalent to multiplication by 2n. There are two left shift instructions in MIPS, sll and sllv.
The shift left logical (sll) instruction has the following format:
sll Rd, Rt, sa
This instruction shifts the value in Rt sa bits to the left, and places the result in Rd. For example, the following instruction shifts the value in $t1 2 bits to the left, and places the result in $t2:
li $t1, 0x00FA24CE # $t1 = 0000 0000 1111 1010 0010 0100 1100 1110
sll $t2, $t1, 2 # $t2 = 0000 0011 1110 1000 1001 0011 0011 1000
The number of bits to shift must be between 0 and 31.
The shift left logical (sllv) instruction has the following format:
sllv Rd, Rt, Rs
This instruction shifts the value in Rt to the left and places the result in Rd. The number of bits to shift is given by the low order 5 bits of Rs, so the number of bits to shift again must be between 0 and 31. For example, the following instruction shifts the value from $t2 2 bits to the left, and places the result in $t3:
li $t1, 2
li $t2, 0x00FA24CE # $t2 = 0000 0000 1111 1010 0010 0100 1100 1110
sllv $t3, $t2, $t1 # $t3 = 0000 0011 1110 1000 1001 0011 0011 1000
There are two types of right shift: logical and arithmetic. Both types shift the bits to the right, and the low order bit is lost. The difference is in what is shifted into the high order bit. In a logical shift, a zero is shifted into the high order bit. In an arithmetic shift, the high order bit is sign extended: the value shifted into the high order bit matches the sign of the number. So if the number is positive, a zero is shifted in, and if the number is negative, then a one is shifted in.
For example, the following is an example of logical right shift:
original: 0011 0100 1101 1110 (0011010011011110)
shift right 1: 0001 1010 0110 1111 (0001101001101111)
shift right 2: 0000 1101 0011 0111 (0000110100110111)
shift right 3: 0000 0110 1001 1011 (0000011010011011)
shift right 4: 0000 0011 0100 1101 (0000001101001101)
If the number is positive, then arithmetic right shift looks just like logical right shift, since 0's are shifted into the high order bits. The following is an example of arithmetic right shift with a negative value:
original: 1111 0100 1101 1110 (1111010011011110)
shift right 1: 1111 1010 0110 1111 (1111101001101111)
shift right 2: 1111 1101 0011 0111 (1111110100110111)
shift right 3: 1111 1110 1001 1011 (1111111010011011)
shift right 4: 1111 1111 0100 1101 (1111111101001101)
Shifting 1 bit to the right is equivalent to integer division by 2. Shifting n bits to the right is sqivalent to division by 2n. However, an arithmetic shift of an odd negative number does not perform the usual truncation. Instead it rounds down to the next negative integer. For example, consider the following (shortened to 8 bits for clarity):
original value: 1111 0111 (-9)
shift right: 1111 1011 (-5)
There are four right shift instructions in MIPS, srl and srlv are the logical shift instructions and sra and srav are the arithmetic shift instructions.
The shift right logical (srl) instruction has the following format:
srl Rd, Rt, sa
This instruction shifts the value in Rt sa bits to the right, and places the result in Rd. Zeros are shifted into the high order positions of Rd. For example, the following instruction shifts the value in $t1 2 bits to the right, and places the result in $t2:
li $t1, 0x00FA24CE # $t1 = 0000 0000 1111 1010 0010 0100 1100 1110
srl $t2, $t1, 2 # $t2 = 0000 0000 0011 1110 1000 1001 0011 0011
The number of bits to shift must be between 0 and 31.
The shift right logical (srlv) instruction has the following format:
srlv Rd, Rt, Rs
This instruction shifts the value in Rt to the right and places the result in Rd. The number of bits to shift is given by the low order 5 bits of Rs, so the number of bits to shift again must be between 0 and 31. Zeros are shifted into the high order positions of Rd. For example, the following instruction shifts the value from $t2 2 bits to the right, and places the result in $t3:
li $t1, 2
li $t2, 0x00FA24CE # $t2 = 0000 0000 1111 1010 0010 0100 1100 1110
srlv $t3, $t2, $t1 # $t3 = 0000 0000 0011 1110 1000 1001 0011 0011
The shift right arithmetic (sra) instruction has the following format:
sra Rd, Rt, sa
This instruction shifts the value in Rt sa bits to the right, and places the result in Rd. The high order positions of Rd are sign extended. For example, the following instruction shifts the value in $t1 2 bits to the right, and places the result in $t2:
li $t1, 0xF6FA24CE # $t1 = 1111 0110 1111 1010 0010 0100 1100 1110
sra $t2, $t1, 2 # $t2 = 1111 1101 1011 1110 1000 1001 0011 0011
The number of bits to shift must be between 0 and 31.
The shift right arithmetic variable (srav) instruction has the following format:
srav Rd, Rt, Rs
This instruction shifts the value in Rt to the right and places the result in Rd. The number of bits to shift is given by the low order 5 bits of Rs, so the number of bits to shift again must be between 0 and 31. The high order positions of Rd are sign extended. For example, the following instruction shifts the value from $t2 2 bits to the right, and places the result in $t3:
li $t1, 2
li $t2, 0xF6FA24CE # $t2 = 1111 0110 1111 1010 0010 0100 1100 1110
srav $t3, $t2, $t1 # $t3 = 1111 1101 1011 1110 1000 1001 0011 0011
Email Me |
Office Hours |
My Home Page |
Department Home |
MCC Home Page
© Copyright Emmi Schatz 2009